9s12d64 -External memory access

classic Classic list List threaded Threaded
6 messages Options
Reply | Threaded
Open this post in threaded view
|

9s12d64 -External memory access

imtiyazfmn
Hello,
I am going t use 9s12d64 for my older design with replacing this.In older design MC68HC11 was used.on that design an FPGA used on 0x8000 to 0x803f adress.So now i wanted to use same adress for an FPGA so is it possible in 9s12d64 controller?
Since i have read that 0x8000 to 0xBFFF is used for program memory using page window.And insight of micro internal flash is available in this location so i am thinking that i can not used for external FPGA access.
So please anyone can suggest that can i used that location for external FPGA access for read and write? if yes please give me setting of internal registor to disble internal flash on that location ?
Also please suggest linker file section to difine it external Read write memory  in cosmic compiler linker file (lkf file).    

Reply | Threaded
Open this post in threaded view
|

Re: 9s12d64 -External memory access

Edward Karpicz
S12D multiplexed external memory interface is not as easy to use as it was
on HC11. What else do you plan to interface with ext.memory bus? If none,
then just bitbang those data, address and CS lines. S12D bus clock is >6
times faster than HC11 with 16MHz crystal. If indeed you need to access a
lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
course you may dislike the need to choose only >=144 pins packages. But
interfacing to S12X memory bus is easy, both codewise and HW-wise.

0x8000 address can be used, but then you will be either limited to 32kB of
nonbanked program memory, or not access your FPGA from banked routines.

Can't help you with Cosmic.

Edward

----- Original Message -----
From: "imtiyazfmn" <[hidden email]>
To: <[hidden email]>
Sent: Thursday, September 08, 2011 10:38 PM
Subject: [68HC12] 9s12d64 -External memory access


> Hello,
> I am going t use 9s12d64 for my older design with replacing this.In older
> design MC68HC11 was used.on that design an FPGA used on 0x8000 to 0x803f
> adress.So now i wanted to use same adress for an FPGA so is it possible in
> 9s12d64 controller?
> Since i have read that 0x8000 to 0xBFFF is used for program memory using
> page window.And insight of micro internal flash is available in this
> location so i am thinking that i can not used for external FPGA access.
> So please anyone can suggest that can i used that location for external
> FPGA access for read and write? if yes please give me setting of internal
> registor to disble internal flash on that location ?
> Also please suggest linker file section to difine it external Read write
> memory  in cosmic compiler linker file (lkf file).
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>

Reply | Threaded
Open this post in threaded view
|

Re: 9s12d64 -External memory access

imtiyazfmn
Thanks for reply..
Actually we will use only FPGA on external bus and my program size is also less then 5k and we don't want to change in firmware (like bitbang ) because decoding logic is insight of FPGA and we will 10MHZ external clock feed to micro with disable internal PLL .
So please suggest me how can i disable flash on ox8000 to 0xBFFF adress location?
If any other thing that i need to confirm please suggest?        

--- In [hidden email], "Edvardas" <karpicz@...> wrote:

>
> S12D multiplexed external memory interface is not as easy to use as it was
> on HC11. What else do you plan to interface with ext.memory bus? If none,
> then just bitbang those data, address and CS lines. S12D bus clock is >6
> times faster than HC11 with 16MHz crystal. If indeed you need to access a
> lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
> course you may dislike the need to choose only >=144 pins packages. But
> interfacing to S12X memory bus is easy, both codewise and HW-wise.
>
> 0x8000 address can be used, but then you will be either limited to 32kB of
> nonbanked program memory, or not access your FPGA from banked routines.
>
> Can't help you with Cosmic.
>
> Edward
>
> ----- Original Message -----
> From: "imtiyazfmn" <imtiyazfmn@...>
> To: <[hidden email]>
> Sent: Thursday, September 08, 2011 10:38 PM
> Subject: [68HC12] 9s12d64 -External memory access
>
>
> > Hello,
> > I am going t use 9s12d64 for my older design with replacing this.In older
> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to 0x803f
> > adress.So now i wanted to use same adress for an FPGA so is it possible in
> > 9s12d64 controller?
> > Since i have read that 0x8000 to 0xBFFF is used for program memory using
> > page window.And insight of micro internal flash is available in this
> > location so i am thinking that i can not used for external FPGA access.
> > So please anyone can suggest that can i used that location for external
> > FPGA access for read and write? if yes please give me setting of internal
> > registor to disble internal flash on that location ?
> > Also please suggest linker file section to difine it external Read write
> > memory  in cosmic compiler linker file (lkf file).
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
> >
>


Reply | Threaded
Open this post in threaded view
|

Re: Re: 9s12d64 -External memory access

Edward Karpicz
Single external device with few addresses? It doesn't make sense to use
external bus on S12D. Bitbanging you could use less pins for the same task.

Since you are going to feed external clock to S12D, don't omit that Vhi of
this signal should be not higher than Vddpll (~2.5V).

You don't need to disable flash on 0x8000, you just need to set PPAGE
register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F will
map internal D64 flash to 0x8000, pages 0-0x3B - external memory.

Edward


----- Original Message -----
From: "imtiyazfmn" <[hidden email]>
To: <[hidden email]>
Sent: Friday, September 09, 2011 4:44 PM
Subject: [68HC12] Re: 9s12d64 -External memory access


> Thanks for reply..
> Actually we will use only FPGA on external bus and my program size is also
> less then 5k and we don't want to change in firmware (like bitbang )
> because decoding logic is insight of FPGA and we will 10MHZ external clock
> feed to micro with disable internal PLL .
> So please suggest me how can i disable flash on ox8000 to 0xBFFF adress
> location?
> If any other thing that i need to confirm please suggest?
>
> --- In [hidden email], "Edvardas" <karpicz@...> wrote:
>>
>> S12D multiplexed external memory interface is not as easy to use as it
>> was
>> on HC11. What else do you plan to interface with ext.memory bus? If none,
>> then just bitbang those data, address and CS lines. S12D bus clock is >6
>> times faster than HC11 with 16MHz crystal. If indeed you need to access a
>> lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
>> course you may dislike the need to choose only >=144 pins packages. But
>> interfacing to S12X memory bus is easy, both codewise and HW-wise.
>>
>> 0x8000 address can be used, but then you will be either limited to 32kB
>> of
>> nonbanked program memory, or not access your FPGA from banked routines.
>>
>> Can't help you with Cosmic.
>>
>> Edward
>>
>> ----- Original Message -----
>> From: "imtiyazfmn" <imtiyazfmn@...>
>> To: <[hidden email]>
>> Sent: Thursday, September 08, 2011 10:38 PM
>> Subject: [68HC12] 9s12d64 -External memory access
>>
>>
>> > Hello,
>> > I am going t use 9s12d64 for my older design with replacing this.In
>> > older
>> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
>> > 0x803f
>> > adress.So now i wanted to use same adress for an FPGA so is it possible
>> > in
>> > 9s12d64 controller?
>> > Since i have read that 0x8000 to 0xBFFF is used for program memory
>> > using
>> > page window.And insight of micro internal flash is available in this
>> > location so i am thinking that i can not used for external FPGA access.
>> > So please anyone can suggest that can i used that location for external
>> > FPGA access for read and write? if yes please give me setting of
>> > internal
>> > registor to disble internal flash on that location ?
>> > Also please suggest linker file section to difine it external Read
>> > write
>> > memory  in cosmic compiler linker file (lkf file).
>> >
>> >
>> >
>> > ------------------------------------
>> >
>> > Yahoo! Groups Links
>> >
>> >
>> >
>>
>
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>

Reply | Threaded
Open this post in threaded view
|

Re: 9s12d64 -External memory access

imtiyazfmn
Can you please suggest me that how can i change PPAGE in my code memory for access external memory?
And also please suggest that how to set PPAGE for 1st time when my device is power on/Reset because its default PPAGE VALUE is zero at reset and my fixed flash is on 3F PPAGE value ? will it automatically set at reset vector location or what?

Imtiyaz

 
--- In [hidden email], "Edvard Karpicz" <karpicz@...> wrote:

>
> Single external device with few addresses? It doesn't make sense to use
> external bus on S12D. Bitbanging you could use less pins for the same task.
>
> Since you are going to feed external clock to S12D, don't omit that Vhi of
> this signal should be not higher than Vddpll (~2.5V).
>
> You don't need to disable flash on 0x8000, you just need to set PPAGE
> register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F will
> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
>
> Edward
>
>
> ----- Original Message -----
> From: "imtiyazfmn" <imtiyazfmn@...>
> To: <[hidden email]>
> Sent: Friday, September 09, 2011 4:44 PM
> Subject: [68HC12] Re: 9s12d64 -External memory access
>
>
> > Thanks for reply..
> > Actually we will use only FPGA on external bus and my program size is also
> > less then 5k and we don't want to change in firmware (like bitbang )
> > because decoding logic is insight of FPGA and we will 10MHZ external clock
> > feed to micro with disable internal PLL .
> > So please suggest me how can i disable flash on ox8000 to 0xBFFF adress
> > location?
> > If any other thing that i need to confirm please suggest?
> >
> > --- In [hidden email], "Edvardas" <karpicz@> wrote:
> >>
> >> S12D multiplexed external memory interface is not as easy to use as it
> >> was
> >> on HC11. What else do you plan to interface with ext.memory bus? If none,
> >> then just bitbang those data, address and CS lines. S12D bus clock is >6
> >> times faster than HC11 with 16MHz crystal. If indeed you need to access a
> >> lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
> >> course you may dislike the need to choose only >=144 pins packages. But
> >> interfacing to S12X memory bus is easy, both codewise and HW-wise.
> >>
> >> 0x8000 address can be used, but then you will be either limited to 32kB
> >> of
> >> nonbanked program memory, or not access your FPGA from banked routines.
> >>
> >> Can't help you with Cosmic.
> >>
> >> Edward
> >>
> >> ----- Original Message -----
> >> From: "imtiyazfmn" <imtiyazfmn@>
> >> To: <[hidden email]>
> >> Sent: Thursday, September 08, 2011 10:38 PM
> >> Subject: [68HC12] 9s12d64 -External memory access
> >>
> >>
> >> > Hello,
> >> > I am going t use 9s12d64 for my older design with replacing this.In
> >> > older
> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
> >> > 0x803f
> >> > adress.So now i wanted to use same adress for an FPGA so is it possible
> >> > in
> >> > 9s12d64 controller?
> >> > Since i have read that 0x8000 to 0xBFFF is used for program memory
> >> > using
> >> > page window.And insight of micro internal flash is available in this
> >> > location so i am thinking that i can not used for external FPGA access.
> >> > So please anyone can suggest that can i used that location for external
> >> > FPGA access for read and write? if yes please give me setting of
> >> > internal
> >> > registor to disble internal flash on that location ?
> >> > Also please suggest linker file section to difine it external Read
> >> > write
> >> > memory  in cosmic compiler linker file (lkf file).
> >> >
> >> >
> >> >
> >> > ------------------------------------
> >> >
> >> > Yahoo! Groups Links
> >> >
> >> >
> >> >
> >>
> >
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
> >
>


Reply | Threaded
Open this post in threaded view
|

Re: Re: 9s12d64 -External memory access

Edward Karpicz
Default PPAGE is 0? That's good news for you, you don't need to do anything.
Your FPGA should be accessible at 0x8000 out of reset in normal expanded
mode.

You said you don't need a lot of flash. So 32kB of nonbanked flash
(0x4000..0x7FFF and 0xC000..0xFFFF) should suffice, right? So no need to
write to PPAGE register.

Edward

----- Original Message -----
From: "imtiyazfmn" <[hidden email]>
To: <[hidden email]>
Sent: Tuesday, September 13, 2011 4:38 PM
Subject: [68HC12] Re: 9s12d64 -External memory access


> Can you please suggest me that how can i change PPAGE in my code memory
> for access external memory?
> And also please suggest that how to set PPAGE for 1st time when my device
> is power on/Reset because its default PPAGE VALUE is zero at reset and my
> fixed flash is on 3F PPAGE value ? will it automatically set at reset
> vector location or what?
>
> Imtiyaz
>
>
> --- In [hidden email], "Edvard Karpicz" <karpicz@...> wrote:
>>
>> Single external device with few addresses? It doesn't make sense to use
>> external bus on S12D. Bitbanging you could use less pins for the same
>> task.
>>
>> Since you are going to feed external clock to S12D, don't omit that Vhi
>> of
>> this signal should be not higher than Vddpll (~2.5V).
>>
>> You don't need to disable flash on 0x8000, you just need to set PPAGE
>> register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F
>> will
>> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
>>
>> Edward
>>
>>
>> ----- Original Message -----
>> From: "imtiyazfmn" <imtiyazfmn@...>
>> To: <[hidden email]>
>> Sent: Friday, September 09, 2011 4:44 PM
>> Subject: [68HC12] Re: 9s12d64 -External memory access
>>
>>
>> > Thanks for reply..
>> > Actually we will use only FPGA on external bus and my program size is
>> > also
>> > less then 5k and we don't want to change in firmware (like bitbang )
>> > because decoding logic is insight of FPGA and we will 10MHZ external
>> > clock
>> > feed to micro with disable internal PLL .
>> > So please suggest me how can i disable flash on ox8000 to 0xBFFF adress
>> > location?
>> > If any other thing that i need to confirm please suggest?
>> >
>> > --- In [hidden email], "Edvardas" <karpicz@> wrote:
>> >>
>> >> S12D multiplexed external memory interface is not as easy to use as it
>> >> was
>> >> on HC11. What else do you plan to interface with ext.memory bus? If
>> >> none,
>> >> then just bitbang those data, address and CS lines. S12D bus clock is
>> >>  >6
>> >> times faster than HC11 with 16MHz crystal. If indeed you need to
>> >> access a
>> >> lot of address space, then better choose S12XD, S12XA or S12XE MCU's.
>> >> Of
>> >> course you may dislike the need to choose only >=144 pins packages.
>> >> But
>> >> interfacing to S12X memory bus is easy, both codewise and HW-wise.
>> >>
>> >> 0x8000 address can be used, but then you will be either limited to
>> >> 32kB
>> >> of
>> >> nonbanked program memory, or not access your FPGA from banked
>> >> routines.
>> >>
>> >> Can't help you with Cosmic.
>> >>
>> >> Edward
>> >>
>> >> ----- Original Message -----
>> >> From: "imtiyazfmn" <imtiyazfmn@>
>> >> To: <[hidden email]>
>> >> Sent: Thursday, September 08, 2011 10:38 PM
>> >> Subject: [68HC12] 9s12d64 -External memory access
>> >>
>> >>
>> >> > Hello,
>> >> > I am going t use 9s12d64 for my older design with replacing this.In
>> >> > older
>> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
>> >> > 0x803f
>> >> > adress.So now i wanted to use same adress for an FPGA so is it
>> >> > possible
>> >> > in
>> >> > 9s12d64 controller?
>> >> > Since i have read that 0x8000 to 0xBFFF is used for program memory
>> >> > using
>> >> > page window.And insight of micro internal flash is available in this
>> >> > location so i am thinking that i can not used for external FPGA
>> >> > access.
>> >> > So please anyone can suggest that can i used that location for
>> >> > external
>> >> > FPGA access for read and write? if yes please give me setting of
>> >> > internal
>> >> > registor to disble internal flash on that location ?
>> >> > Also please suggest linker file section to difine it external Read
>> >> > write
>> >> > memory  in cosmic compiler linker file (lkf file).
>> >> >
>> >> >
>> >> >
>> >> > ------------------------------------
>> >> >
>> >> > Yahoo! Groups Links
>> >> >
>> >> >
>> >> >
>> >>
>> >
>> >
>> >
>> >
>> > ------------------------------------
>> >
>> > Yahoo! Groups Links
>> >
>> >
>> >
>>
>
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>