[EE] Four Layer Routing Strategy

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[EE] Four Layer Routing Strategy

Josh Koffman
Hi all,

I'm working on my first 4 layer board. I feel a bit like I failed
cramming it all into two layers, but I recognize that having so many
vias on every trace would be less than ideal.

I'm using top and bottom for signals, then the inner layers for power.
The board isn't anything crazy RF, just some regular digital signals.
There is some digital audio on the board, so there are a few "medium"
frequency traces.

I plan on using the top inner layer for ground. I'll do it like I
normally do, which is to route the ground traces manually, then do a
pour that connects to the ground trace in one place.

On the bottom inner layer I'm going to route my 3.3V traces. There
will be a lot of free space on that layer.

So the question is, what should I do with the free space on the 3.3V
layer? I could do either a 3.3V pour or another ground pour. I lean
towards another ground pour but I don't want to inadvertently create a
weird capacitor.

Any suggestions? Since this is my first time I'd like to not have to
re-make the board because of this particular error!

Thank you!

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
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Re: [EE] Four Layer Routing Strategy

David C Brown
The most complex board I designed just before retiring had 14 layers which
had several power and ground planes (and which worked well at
several hundred meg)
I never mixed ground and power on a single layer though I might have more
than one voltage plane on a layer.

So I would advise you to have a solid 3.3 volt plane on layer 3.  That way
you are running your signals on both outer layers over a plane; you are
reducing the impedance of the 3.3 volt distribution; and you are providing
a useful distributed decoupling capacitor
__________________________________________
David C Brown
43 Bings Road
Whaley Bridge
High Peak                           Phone: 01663 733236
Derbyshire                eMail: [hidden email]
SK23 7ND          web: www.bings-knowle.co.uk/dcb
<http://www.jb.man.ac.uk/~dcb>



*Sent from my etch-a-sketch*


On Sat, 12 Sep 2020 at 18:13, Josh Koffman <[hidden email]> wrote:

> Hi all,
>
> I'm working on my first 4 layer board. I feel a bit like I failed
> cramming it all into two layers, but I recognize that having so many
> vias on every trace would be less than ideal.
>
> I'm using top and bottom for signals, then the inner layers for power.
> The board isn't anything crazy RF, just some regular digital signals.
> There is some digital audio on the board, so there are a few "medium"
> frequency traces.
>
> I plan on using the top inner layer for ground. I'll do it like I
> normally do, which is to route the ground traces manually, then do a
> pour that connects to the ground trace in one place.
>
> On the bottom inner layer I'm going to route my 3.3V traces. There
> will be a lot of free space on that layer.
>
> So the question is, what should I do with the free space on the 3.3V
> layer? I could do either a 3.3V pour or another ground pour. I lean
> towards another ground pour but I don't want to inadvertently create a
> weird capacitor.
>
> Any suggestions? Since this is my first time I'd like to not have to
> re-make the board because of this particular error!
>
> Thank you!
>
> Josh
> --
> A common mistake that people make when trying to design something
> completely foolproof is to underestimate the ingenuity of complete
> fools.
>         -Douglas Adams
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
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Re: [EE] Four Layer Routing Strategy

Bob Blick-5
In reply to this post by Josh Koffman
Hi Josh,

If you can use layer 2 for ground and layer 3 for +3.3 then you are getting the best possible compromise. I say compromise only because having all your routing on inner layers with buried vias is probably theoretically better, but it would be a ridiculously dumb thing in the real world.

Friendly regards, Bob

________________________________________
From: [hidden email] <[hidden email]> on behalf of Josh Koffman
Sent: Saturday, September 12, 2020 10:10 AM
To: Microcontroller discussion list - Public.
Subject: [EE] Four Layer Routing Strategy

Hi all,

I'm working on my first 4 layer board. I feel a bit like I failed
cramming it all into two layers, but I recognize that having so many
vias on every trace would be less than ideal.

I'm using top and bottom for signals, then the inner layers for power.
The board isn't anything crazy RF, just some regular digital signals.
There is some digital audio on the board, so there are a few "medium"
frequency traces.

I plan on using the top inner layer for ground. I'll do it like I
normally do, which is to route the ground traces manually, then do a
pour that connects to the ground trace in one place.

On the bottom inner layer I'm going to route my 3.3V traces. There
will be a lot of free space on that layer.

So the question is, what should I do with the free space on the 3.3V
layer? I could do either a 3.3V pour or another ground pour. I lean
towards another ground pour but I don't want to inadvertently create a
weird capacitor.

Any suggestions? Since this is my first time I'd like to not have to
re-make the board because of this particular error!

Thank you!

Josh


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Re: [EE] Four Layer Routing Strategy

David C Brown
In my experience routing on inner layers is best avoided  unless absolutely
necessary - which it won't be on the board Josh describes.

And, quite apart from the practical problems caused by buried vias, a board
with them is considerably more expensive to produce.

Takjing theory and practice together having planes on the inner layers of a
four layer board is no compromise
__________________________________________
David C Brown
43 Bings Road
Whaley Bridge
High Peak                           Phone: 01663 733236
Derbyshire                eMail: [hidden email]
SK23 7ND          web: www.bings-knowle.co.uk/dcb
<http://www.jb.man.ac.uk/~dcb>



*Sent from my etch-a-sketch*


On Sat, 12 Sep 2020 at 18:53, Bob Blick <[hidden email]> wrote:

> Hi Josh,
>
> If you can use layer 2 for ground and layer 3 for +3.3 then you are
> getting the best possible compromise. I say compromise only because having
> all your routing on inner layers with buried vias is probably theoretically
> better, but it would be a ridiculously dumb thing in the real world.
>
> Friendly regards, Bob
>
> ________________________________________
> From: [hidden email] <[hidden email]> on behalf of Josh
> Koffman
> Sent: Saturday, September 12, 2020 10:10 AM
> To: Microcontroller discussion list - Public.
> Subject: [EE] Four Layer Routing Strategy
>
> Hi all,
>
> I'm working on my first 4 layer board. I feel a bit like I failed
> cramming it all into two layers, but I recognize that having so many
> vias on every trace would be less than ideal.
>
> I'm using top and bottom for signals, then the inner layers for power.
> The board isn't anything crazy RF, just some regular digital signals.
> There is some digital audio on the board, so there are a few "medium"
> frequency traces.
>
> I plan on using the top inner layer for ground. I'll do it like I
> normally do, which is to route the ground traces manually, then do a
> pour that connects to the ground trace in one place.
>
> On the bottom inner layer I'm going to route my 3.3V traces. There
> will be a lot of free space on that layer.
>
> So the question is, what should I do with the free space on the 3.3V
> layer? I could do either a 3.3V pour or another ground pour. I lean
> towards another ground pour but I don't want to inadvertently create a
> weird capacitor.
>
> Any suggestions? Since this is my first time I'd like to not have to
> re-make the board because of this particular error!
>
> Thank you!
>
> Josh
>
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
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Re: [EE] Four Layer Routing Strategy

Randy Dawson
In reply to this post by Josh Koffman
Hi Josh,

Lets simplify things.
Use your two inner layers for the ground and power (your 3.3V)
The top and bottom are for your signal routes.
A strategy to use, would be for one layer, the top, to be horizontal traces, and the bottom to be the vertical traces.
It is called 'Manhattan routing'.
Its just like driving in the city, you go as far as you can to your destination (on top), turn the corner (drop a via) to the bottom, to go vertical to complete the route your destination.

Randy

________________________________
From: [hidden email] <[hidden email]> on behalf of Josh Koffman <[hidden email]>
Sent: Saturday, September 12, 2020 10:10 AM
To: Microcontroller discussion list - Public. <[hidden email]>
Subject: [EE] Four Layer Routing Strategy

Hi all,

I'm working on my first 4 layer board. I feel a bit like I failed
cramming it all into two layers, but I recognize that having so many
vias on every trace would be less than ideal.

I'm using top and bottom for signals, then the inner layers for power.
The board isn't anything crazy RF, just some regular digital signals.
There is some digital audio on the board, so there are a few "medium"
frequency traces.

I plan on using the top inner layer for ground. I'll do it like I
normally do, which is to route the ground traces manually, then do a
pour that connects to the ground trace in one place.

On the bottom inner layer I'm going to route my 3.3V traces. There
will be a lot of free space on that layer.

So the question is, what should I do with the free space on the 3.3V
layer? I could do either a 3.3V pour or another ground pour. I lean
towards another ground pour but I don't want to inadvertently create a
weird capacitor.

Any suggestions? Since this is my first time I'd like to not have to
re-make the board because of this particular error!

Thank you!

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
        -Douglas Adams
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
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Re: [EE] Four Layer Routing Strategy

Josh Koffman
In reply to this post by David C Brown
Thank you all for the advice!

Ok, sounds like keeping the inner layers as ground and 3.3V separately
will be the best. No problems there.

One thing about planes though, I once read an article about being
careful using planes, that essentially small ground loops could form
in them. Since then I've always had my planes as a separate net (ie
not ground), and I connected them to the ground traces strategically.
Each area of pour had only one connection to ground.

Should I be using the pours a bit more liberally and letting them join
all the pins on that actual net? That's easily done (actually easier
than the way I have been doing it). I'd add thermals in to try to help
make it easier to solder.

The board service I've been using lately doesn't allow for
blind/buried vias without a hefty upcharge. I am definitely not at
that level, that's for sure!

Thank you!

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
        -Douglas Adams
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Re: [EE] Four Layer Routing Strategy

David C Brown
Don't believe every thing you read on the internet  - except on PIClist :-)
I have never  had problems with ground plane loops and would advise you to
use pours.
__________________________________________
David C Brown
43 Bings Road
Whaley Bridge
High Peak                           Phone: 01663 733236
Derbyshire                eMail: [hidden email]
SK23 7ND          web: www.bings-knowle.co.uk/dcb
<http://www.jb.man.ac.uk/~dcb>



*Sent from my etch-a-sketch*


On Sun, 13 Sep 2020 at 02:57, Josh Koffman <[hidden email]> wrote:

> Thank you all for the advice!
>
> Ok, sounds like keeping the inner layers as ground and 3.3V separately
> will be the best. No problems there.
>
> One thing about planes though, I once read an article about being
> careful using planes, that essentially small ground loops could form
> in them. Since then I've always had my planes as a separate net (ie
> not ground), and I connected them to the ground traces strategically.
> Each area of pour had only one connection to ground.
>
> Should I be using the pours a bit more liberally and letting them join
> all the pins on that actual net? That's easily done (actually easier
> than the way I have been doing it). I'd add thermals in to try to help
> make it easier to solder.
>
> The board service I've been using lately doesn't allow for
> blind/buried vias without a hefty upcharge. I am definitely not at
> that level, that's for sure!
>
> Thank you!
>
> Josh
> --
> A common mistake that people make when trying to design something
> completely foolproof is to underestimate the ingenuity of complete
> fools.
>         -Douglas Adams
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
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Re: [EE] Four Layer Routing Strategy

Alan Pearce
In reply to this post by Josh Koffman
> Ok, sounds like keeping the inner layers as ground and 3.3V separately
> will be the best. No problems there.

That is the 'normal' way to do it. And using manhattan routing gives
you a good starting point. Once you have the board routed you can look
to see where the routing can be tweaked to minimise vias.

> One thing about planes though, I once read an article about being
> careful using planes, that essentially small ground loops could form
> in them.

Opinion on this has gone back and forth like a leaf in the wind, but
one of the most authoritative texts I have seen was an appnote or
article from ADI which advocated having one complete ground plane with
minimal distinction between digital and analogue ground. It doesn't
mean you could mix the digital and analogue parts willy nilly, some
care is still needed with relative parts placement.

On Sun, 13 Sep 2020 at 02:57, Josh Koffman <[hidden email]> wrote:

>
> Thank you all for the advice!
>
> Ok, sounds like keeping the inner layers as ground and 3.3V separately
> will be the best. No problems there.
>
> One thing about planes though, I once read an article about being
> careful using planes, that essentially small ground loops could form
> in them. Since then I've always had my planes as a separate net (ie
> not ground), and I connected them to the ground traces strategically.
> Each area of pour had only one connection to ground.
>
> Should I be using the pours a bit more liberally and letting them join
> all the pins on that actual net? That's easily done (actually easier
> than the way I have been doing it). I'd add thermals in to try to help
> make it easier to solder.
>
> The board service I've been using lately doesn't allow for
> blind/buried vias without a hefty upcharge. I am definitely not at
> that level, that's for sure!
>
> Thank you!
>
> Josh
> --
> A common mistake that people make when trying to design something
> completely foolproof is to underestimate the ingenuity of complete
> fools.
>         -Douglas Adams
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
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Re: [EE] Four Layer Routing Strategy

Luis Moreira-5
Hi All,
I've been doing a bit of PCB layout lately, I'm actually doing a 500KHZ
bandwidth analogue optical link at the moment. Obviously noise issues are
very high on my list of issues to avoid.
The layout strategy you are describing seems very good, but I gave a few
questions:

- What do you do with through hole components?

- how do you deal with a surface mode power supply for the circuit board?
You will have to place it on the top routing layer  but do you immediately
get vias to the power layers?

- The vias crossing from the routing layers through the power layers, will
this  not create other issues?

On a sightly different subject, on a two layer board I tend to run power
and routing on the top layer and ground layer mostly as a copper poor on
the bottom layer, is this best practice?

Thank you.
Best Regards
               Luis

On Sun, 13 Sep 2020, 12:57 Alan Pearce, <[hidden email]>
wrote:

> > Ok, sounds like keeping the inner layers as ground and 3.3V separately
> > will be the best. No problems there.
>
> That is the 'normal' way to do it. And using manhattan routing gives
> you a good starting point. Once you have the board routed you can look
> to see where the routing can be tweaked to minimise vias.
>
> > One thing about planes though, I once read an article about being
> > careful using planes, that essentially small ground loops could form
> > in them.
>
> Opinion on this has gone back and forth like a leaf in the wind, but
> one of the most authoritative texts I have seen was an appnote or
> article from ADI which advocated having one complete ground plane with
> minimal distinction between digital and analogue ground. It doesn't
> mean you could mix the digital and analogue parts willy nilly, some
> care is still needed with relative parts placement.
>
> On Sun, 13 Sep 2020 at 02:57, Josh Koffman <[hidden email]> wrote:
> >
> > Thank you all for the advice!
> >
> > Ok, sounds like keeping the inner layers as ground and 3.3V separately
> > will be the best. No problems there.
> >
> > One thing about planes though, I once read an article about being
> > careful using planes, that essentially small ground loops could form
> > in them. Since then I've always had my planes as a separate net (ie
> > not ground), and I connected them to the ground traces strategically.
> > Each area of pour had only one connection to ground.
> >
> > Should I be using the pours a bit more liberally and letting them join
> > all the pins on that actual net? That's easily done (actually easier
> > than the way I have been doing it). I'd add thermals in to try to help
> > make it easier to solder.
> >
> > The board service I've been using lately doesn't allow for
> > blind/buried vias without a hefty upcharge. I am definitely not at
> > that level, that's for sure!
> >
> > Thank you!
> >
> > Josh
> > --
> > A common mistake that people make when trying to design something
> > completely foolproof is to underestimate the ingenuity of complete
> > fools.
> >         -Douglas Adams
> > --
> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
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>
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Re: [EE] Four Layer Routing Strategy

Alan Pearce
> - What do you do with through hole components?

well, they still have holes through the PCB as done in the past. If
one end is connected to power or ground then the via will connect to
the appropriate plane with thermal reliefs.

> - how do you deal with a surface mode power supply for the circuit board?
> You will have to place it on the top routing layer  but do you immediately
> get vias to the power layers?

Are you talking a prebuilt module here or are you looking at regulator
IC? Either way the manufacturer will generally have a recommended PCB
layout.

> - The vias crossing from the routing layers through the power layers, will
> this  not create other issues?

Depends on what you regard as issues. Yes on a high speed circuit such
as gigabit video then a via becomes a stub that imparts some extra
inductance that may have to be balanced out in some way, but such
signals are normally run as differential signals as they will be
impedance controlled. You talk of doing 500kHz bandwidth, but what is
your effective carrier frequency, or are you talking in terms of a
500kbaud signal? In the latter case i wouldn't expect vias to be a
problem, but if you are working with a higher frequency carrier then
you may need to be more careful with routing.

The thing with vias going through power layers is to make sure you set
up your constraints so that there is sufficient clearance around the
via that production tolerances don't produce a short to the plane due
to drilling tolerances. And ALWAYS use thermal reliefs to any plane or
fill on any layer.


On Sun, 13 Sep 2020 at 13:29, Luis Moreira
<[hidden email]> wrote:

>
> Hi All,
> I've been doing a bit of PCB layout lately, I'm actually doing a 500KHZ
> bandwidth analogue optical link at the moment. Obviously noise issues are
> very high on my list of issues to avoid.
> The layout strategy you are describing seems very good, but I gave a few
> questions:
>
> - What do you do with through hole components?
>
> - how do you deal with a surface mode power supply for the circuit board?
> You will have to place it on the top routing layer  but do you immediately
> get vias to the power layers?
>
> - The vias crossing from the routing layers through the power layers, will
> this  not create other issues?
>
> On a sightly different subject, on a two layer board I tend to run power
> and routing on the top layer and ground layer mostly as a copper poor on
> the bottom layer, is this best practice?
>
> Thank you.
> Best Regards
>                Luis
>
> On Sun, 13 Sep 2020, 12:57 Alan Pearce, <[hidden email]>
> wrote:
>
> > > Ok, sounds like keeping the inner layers as ground and 3.3V separately
> > > will be the best. No problems there.
> >
> > That is the 'normal' way to do it. And using manhattan routing gives
> > you a good starting point. Once you have the board routed you can look
> > to see where the routing can be tweaked to minimise vias.
> >
> > > One thing about planes though, I once read an article about being
> > > careful using planes, that essentially small ground loops could form
> > > in them.
> >
> > Opinion on this has gone back and forth like a leaf in the wind, but
> > one of the most authoritative texts I have seen was an appnote or
> > article from ADI which advocated having one complete ground plane with
> > minimal distinction between digital and analogue ground. It doesn't
> > mean you could mix the digital and analogue parts willy nilly, some
> > care is still needed with relative parts placement.
> >
> > On Sun, 13 Sep 2020 at 02:57, Josh Koffman <[hidden email]> wrote:
> > >
> > > Thank you all for the advice!
> > >
> > > Ok, sounds like keeping the inner layers as ground and 3.3V separately
> > > will be the best. No problems there.
> > >
> > > One thing about planes though, I once read an article about being
> > > careful using planes, that essentially small ground loops could form
> > > in them. Since then I've always had my planes as a separate net (ie
> > > not ground), and I connected them to the ground traces strategically.
> > > Each area of pour had only one connection to ground.
> > >
> > > Should I be using the pours a bit more liberally and letting them join
> > > all the pins on that actual net? That's easily done (actually easier
> > > than the way I have been doing it). I'd add thermals in to try to help
> > > make it easier to solder.
> > >
> > > The board service I've been using lately doesn't allow for
> > > blind/buried vias without a hefty upcharge. I am definitely not at
> > > that level, that's for sure!
> > >
> > > Thank you!
> > >
> > > Josh
> > > --
> > > A common mistake that people make when trying to design something
> > > completely foolproof is to underestimate the ingenuity of complete
> > > fools.
> > >         -Douglas Adams
> > > --
> > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > > View/change your membership options at
> > > http://mailman.mit.edu/mailman/listinfo/piclist
> > --
> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
> >
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Re: [EE] Four Layer Routing Strategy

Luis Moreira-5
Hi Alan,

I can see for through-hole components in essence it will be really strait
forward.

I'm using a traco power DC to DC converter with  +15V/ -15V output which is
surface mount. It will be on the top layer. After dealing with it's layout
requirements, I need then to distribute power as required. so my question
was since I'm on the top layer should I try to route power on the top or
just use a via to connect into the internal power layer and distribut that
way.
Also if you have two or 3 voltages on the circuit do you use the power
layer to route all three.

The 500KHz is the bandwidth of the analogue signal which will be
transmitted as a pulse width modulation. This is actually based on an old
silabs technical note. Instead of using one of their isolation ICs I'm
using fibre optics.
I have it working but picked up some noise from the DC to DC converter, do
to my not so good layout around it. I need to redesign the board and I'm
looking for best options.

Thank you.
Best Regards
              Luis

On Sun, 13 Sep 2020, 18:28 Alan Pearce, <[hidden email]>
wrote:

> > - What do you do with through hole components?
>
> well, they still have holes through the PCB as done in the past. If
> one end is connected to power or ground then the via will connect to
> the appropriate plane with thermal reliefs.
>
> > - how do you deal with a surface mode power supply for the circuit board?
> > You will have to place it on the top routing layer  but do you
> immediately
> > get vias to the power layers?
>
> Are you talking a prebuilt module here or are you looking at regulator
> IC? Either way the manufacturer will generally have a recommended PCB
> layout.
>
> > - The vias crossing from the routing layers through the power layers,
> will
> > this  not create other issues?
>
> Depends on what you regard as issues. Yes on a high speed circuit such
> as gigabit video then a via becomes a stub that imparts some extra
> inductance that may have to be balanced out in some way, but such
> signals are normally run as differential signals as they will be
> impedance controlled. You talk of doing 500kHz bandwidth, but what is
> your effective carrier frequency, or are you talking in terms of a
> 500kbaud signal? In the latter case i wouldn't expect vias to be a
> problem, but if you are working with a higher frequency carrier then
> you may need to be more careful with routing.
>
> The thing with vias going through power layers is to make sure you set
> up your constraints so that there is sufficient clearance around the
> via that production tolerances don't produce a short to the plane due
> to drilling tolerances. And ALWAYS use thermal reliefs to any plane or
> fill on any layer.
>
>
> On Sun, 13 Sep 2020 at 13:29, Luis Moreira
> <[hidden email]> wrote:
> >
> > Hi All,
> > I've been doing a bit of PCB layout lately, I'm actually doing a 500KHZ
> > bandwidth analogue optical link at the moment. Obviously noise issues are
> > very high on my list of issues to avoid.
> > The layout strategy you are describing seems very good, but I gave a few
> > questions:
> >
> > - What do you do with through hole components?
> >
> > - how do you deal with a surface mode power supply for the circuit board?
> > You will have to place it on the top routing layer  but do you
> immediately
> > get vias to the power layers?
> >
> > - The vias crossing from the routing layers through the power layers,
> will
> > this  not create other issues?
> >
> > On a sightly different subject, on a two layer board I tend to run power
> > and routing on the top layer and ground layer mostly as a copper poor on
> > the bottom layer, is this best practice?
> >
> > Thank you.
> > Best Regards
> >                Luis
> >
> > On Sun, 13 Sep 2020, 12:57 Alan Pearce, <[hidden email]>
> > wrote:
> >
> > > > Ok, sounds like keeping the inner layers as ground and 3.3V
> separately
> > > > will be the best. No problems there.
> > >
> > > That is the 'normal' way to do it. And using manhattan routing gives
> > > you a good starting point. Once you have the board routed you can look
> > > to see where the routing can be tweaked to minimise vias.
> > >
> > > > One thing about planes though, I once read an article about being
> > > > careful using planes, that essentially small ground loops could form
> > > > in them.
> > >
> > > Opinion on this has gone back and forth like a leaf in the wind, but
> > > one of the most authoritative texts I have seen was an appnote or
> > > article from ADI which advocated having one complete ground plane with
> > > minimal distinction between digital and analogue ground. It doesn't
> > > mean you could mix the digital and analogue parts willy nilly, some
> > > care is still needed with relative parts placement.
> > >
> > > On Sun, 13 Sep 2020 at 02:57, Josh Koffman <[hidden email]>
> wrote:
> > > >
> > > > Thank you all for the advice!
> > > >
> > > > Ok, sounds like keeping the inner layers as ground and 3.3V
> separately
> > > > will be the best. No problems there.
> > > >
> > > > One thing about planes though, I once read an article about being
> > > > careful using planes, that essentially small ground loops could form
> > > > in them. Since then I've always had my planes as a separate net (ie
> > > > not ground), and I connected them to the ground traces strategically.
> > > > Each area of pour had only one connection to ground.
> > > >
> > > > Should I be using the pours a bit more liberally and letting them
> join
> > > > all the pins on that actual net? That's easily done (actually easier
> > > > than the way I have been doing it). I'd add thermals in to try to
> help
> > > > make it easier to solder.
> > > >
> > > > The board service I've been using lately doesn't allow for
> > > > blind/buried vias without a hefty upcharge. I am definitely not at
> > > > that level, that's for sure!
> > > >
> > > > Thank you!
> > > >
> > > > Josh
> > > > --
> > > > A common mistake that people make when trying to design something
> > > > completely foolproof is to underestimate the ingenuity of complete
> > > > fools.
> > > >         -Douglas Adams
> > > > --
> > > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > > > View/change your membership options at
> > > > http://mailman.mit.edu/mailman/listinfo/piclist
> > > --
> > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > > View/change your membership options at
> > > http://mailman.mit.edu/mailman/listinfo/piclist
> > >
> > --
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> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
> --
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>
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Re: [EE] Four Layer Routing Strategy

madscientistatlarge
In reply to this post by Alan Pearce
There's now available from several manufacturers that's basically powdered ferite  mix with silicone rubber and mad into adhesive sheet.  It's used in trouble spots to basically short out the magnetic field because it's high permeability.  I've seen it in cell phones and lap tops in smallish peaces.  It might be worth checking into weather you redesign the board or not, it could possibly save you from the chore of doing a new layout.  I have no information on what this magic rubber cost but it should not be terribly expensive.  It likely could also be used to better shield the dc-dc converter.


Sent with ProtonMail Secure Email.

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Sunday, September 13, 2020 11:21 AM, Alan Pearce <[hidden email]> wrote:

> > -   What do you do with through hole components?
>
> well, they still have holes through the PCB as done in the past. If
> one end is connected to power or ground then the via will connect to
> the appropriate plane with thermal reliefs.
>
> > -   how do you deal with a surface mode power supply for the circuit board?
> >     You will have to place it on the top routing layer but do you immediately
> >     get vias to the power layers?
> >
>
> Are you talking a prebuilt module here or are you looking at regulator
> IC? Either way the manufacturer will generally have a recommended PCB
> layout.
>
> > -   The vias crossing from the routing layers through the power layers, will
> >     this not create other issues?
> >
>
> Depends on what you regard as issues. Yes on a high speed circuit such
> as gigabit video then a via becomes a stub that imparts some extra
> inductance that may have to be balanced out in some way, but such
> signals are normally run as differential signals as they will be
> impedance controlled. You talk of doing 500kHz bandwidth, but what is
> your effective carrier frequency, or are you talking in terms of a
> 500kbaud signal? In the latter case i wouldn't expect vias to be a
> problem, but if you are working with a higher frequency carrier then
> you may need to be more careful with routing.
>
> The thing with vias going through power layers is to make sure you set
> up your constraints so that there is sufficient clearance around the
> via that production tolerances don't produce a short to the plane due
> to drilling tolerances. And ALWAYS use thermal reliefs to any plane or
> fill on any layer.
>
> On Sun, 13 Sep 2020 at 13:29, Luis Moreira
> [hidden email] wrote:
>
> > Hi All,
> > I've been doing a bit of PCB layout lately, I'm actually doing a 500KHZ
> > bandwidth analogue optical link at the moment. Obviously noise issues are
> > very high on my list of issues to avoid.
> > The layout strategy you are describing seems very good, but I gave a few
> > questions:
> >
> > -   What do you do with through hole components?
> >
> > -   how do you deal with a surface mode power supply for the circuit board?
> >     You will have to place it on the top routing layer but do you immediately
> >     get vias to the power layers?
> >
> > -   The vias crossing from the routing layers through the power layers, will
> >     this not create other issues?
> >
> >
> > On a sightly different subject, on a two layer board I tend to run power
> > and routing on the top layer and ground layer mostly as a copper poor on
> > the bottom layer, is this best practice?
> > Thank you.
> > Best Regards
> > Luis
> > On Sun, 13 Sep 2020, 12:57 Alan Pearce, [hidden email]
> > wrote:
> >
> > > > Ok, sounds like keeping the inner layers as ground and 3.3V separately
> > > > will be the best. No problems there.
> > >
> > > That is the 'normal' way to do it. And using manhattan routing gives
> > > you a good starting point. Once you have the board routed you can look
> > > to see where the routing can be tweaked to minimise vias.
> > >
> > > > One thing about planes though, I once read an article about being
> > > > careful using planes, that essentially small ground loops could form
> > > > in them.
> > >
> > > Opinion on this has gone back and forth like a leaf in the wind, but
> > > one of the most authoritative texts I have seen was an appnote or
> > > article from ADI which advocated having one complete ground plane with
> > > minimal distinction between digital and analogue ground. It doesn't
> > > mean you could mix the digital and analogue parts willy nilly, some
> > > care is still needed with relative parts placement.
> > > On Sun, 13 Sep 2020 at 02:57, Josh Koffman [hidden email] wrote:
> > >
> > > > Thank you all for the advice!
> > > > Ok, sounds like keeping the inner layers as ground and 3.3V separately
> > > > will be the best. No problems there.
> > > > One thing about planes though, I once read an article about being
> > > > careful using planes, that essentially small ground loops could form
> > > > in them. Since then I've always had my planes as a separate net (ie
> > > > not ground), and I connected them to the ground traces strategically.
> > > > Each area of pour had only one connection to ground.
> > > > Should I be using the pours a bit more liberally and letting them join
> > > > all the pins on that actual net? That's easily done (actually easier
> > > > than the way I have been doing it). I'd add thermals in to try to help
> > > > make it easier to solder.
> > > > The board service I've been using lately doesn't allow for
> > > > blind/buried vias without a hefty upcharge. I am definitely not at
> > > > that level, that's for sure!
> > > > Thank you!
> > > >
> > > > Josh
> > > >
> > > > -----
> > > >
> > > > A common mistake that people make when trying to design something
> > > > completely foolproof is to underestimate the ingenuity of complete
> > > > fools.
> > > > -Douglas Adams
> > > >
> > > > -----------------------------------------------------------------------------------------------------------------------------------------------------------
> > > >
> > > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > > > View/change your membership options at
> > > > http://mailman.mit.edu/mailman/listinfo/piclist
> > > > --
> > > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > > > View/change your membership options at
> > > > http://mailman.mit.edu/mailman/listinfo/piclist
> >
> > --
> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
>
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> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist



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