Help with the SEC on an MCF5485

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Help with the SEC on an MCF5485

Edwards, James - Centrilift
Help with the SEC on an MCF5485


       From: James Edwards <jamesDOTedwardsATcentriliftDOTcom>

         To: [hidden email]


    Help with the SEC on an MCF5485


Hi WildeRice Gang,

This is my first post.  I was pointed here by Bob McMillan at Future Electronics.  He said a lot of good things about the list.

My Problem is that I’m having some grief figuring out how to use the Security Encryption Controller (SEC) on the MCF5485.

I’ve asked for some help on the FreeScale Forum but have not received any so I’m sending this to out you. In the hope that some of you have already conquered the SEC.  I would like to use the SEC to calculate an MD5 check sum for a file.

You can check out my post, and all my replied to myself on the FreeScale Message board at the link below (I Hope it is OK to link to their message board on the wildrice list)

I’ve pasted a few snippets of C code in there.  It’s getting too long to paste into an email.  If you want to / need to see the source files let me know and I’ll send them to you.

As of today I’ve stopped statically assigning both Crypto channels to the MDEU during initialization because I was getting a channel already assigned error.  I think the Header for the first Descriptor just goes out and grabs the MDEU if it is not already in use anyway.

Now I’m stuck just after loading Fetch Register Zero (FR0) with a pointer to the Head of my first Descriptor (the Descriptor structure and how Im building the Descriptor chain are on the link above) I’m not seeing a done bit or an error bit set in SEC Interrupt Status Register High (SISRH).  When I hit a break point in Debug using CodeWarrior 6.4’s View \ Register Details, I can see my first Descriptor in the Crypto-Channel Descriptor Buffer for Channel Zero (CBUF0) but it will not move on to the next Descriptor in the chain even though the Pointer to the “Next Descriptor” in the chain looks correct to me.  And the CCPSRH0 seems to be stuck in state 0x1B.

Also do Crypto-Channel Zero and channel One really share the same Descriptor Buffer MBAR+ 0x22080-0x220BF ???  I’m only asking because I think I’ve found an error in Rev 4 of the Reference manual.  See the link above for more on that.

I sure could use a nudge in the right direction.

Thanks for any advice you can give me on this.


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