I've been thinking about this one for a while. Basically, If I
interpret the datasheet correctly (16F87X), one should set PR2 to 0xFE *not* 0xFF to get a correct 0-255 PWM value (or 1023 or whatever, I'll be dealing with 8-bit PWM here to make things simpler, but this applies the same way if you take into account the extra 2 bits). I'm not sure if this has ever been mentioned before, but I'm posting it to see if anyone knows anything about this. The reason is, PR2=0xFF would create 256 PWM cycles (always PR2+1 since it resets to 0 on the *next* increment cycle, which is why TIMER2 increments the whole 0x00-0xFF when PR2=0xFF and doesn't skip 0xFF). But for a 255-value PWM you need *255* cycles, since 0% would be all off and 100% would be all on. If PR2=0xFF that creates *256* PWM cycles, of which one would always be a 0. In other words, with 0xFF loaded into CCPRxL, that would output 255/256 overall PWM power, not 255/255 (nor 256/256). To be sure I wasn't getting this all wrong (my brain started to melt a bit while thinking about this), I wrote a short Python program that mimics the behavior of the PIC as stated in the datasheet, and it behaves as I thought it would. To put it another way, if PR2=0, then TIMER2 would continually reset to 0, but you would still have a single PWM cycle which you could control with CCPRxL=0x00 or 0x01. I.e. the number of PWM cycles is PR2+1, which I think means PR2 should be 0xFE for full 255-step (or 1023-step, it applies the same way) PWM. Here's a sample output from my program with PR2=0xFF and CCPRxL=0xFF: TMR2: FE FF 00 01 02 // FD FE FF 00 01 02 // FD FE FF 00 01 02 PIN: 1 0 1 1 1 // 1 1 0 1 1 1 // 1 1 0 1 1 1 I.e. 255 periods PIN=1 and 1 period PIN=0. Any thoughts on this? Does anyone know if this really works this way on the silicon? -- Hector Martin ([hidden email]) Public Key: http://www.marcansoft.com/hector.asc -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist |
Hector Martin wrote:
> But for a 255-value PWM you need *255* cycles, Not quite. A *256* value PWM needs 255 cycles. The kind of off by one issue you mention is common to most quantized dithering schemes. ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist |
Olin Lathrop wrote:
> Hector Martin wrote: >> But for a 255-value PWM you need *255* cycles, > > Not quite. A *256* value PWM needs 255 cycles. Sorry, I meant there something like for a 255-maximum-value (0-255 or 256 value) PWM you need 255 cycles. -- Hector Martin ([hidden email]) Public Key: http://www.marcansoft.com/hector.asc -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist |
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