trouble with PLL on the HC12

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trouble with PLL on the HC12

elgrip
Hello; I am using an ICC12 compiler and NOICE debugger with a USB pod with an HC12 128kB chip running with a 16MHz crystal.

My problem is that when I try to set the PLL up for about 40MHz, the code does not seem to work in the way it should and I can't get a LOCK - or even a TRACK signal.

I have to turn off the PLLSEL bit before trying to set up the mult and divide registers and turning the PLL on, then looking for a LOCK signal; but the manual says that a write to PLLSEL is not possible if the LOCK and TRACK bits are zero.

Does that mean a write 1, or any write? To turn PLLSEL off I need to clear that bit whether I am locked / tracked or not.

In addition, even if I assume I can write a zero to PLLSEL, and even if I have wait loops after setting the mult and divide registers, and then wait in a loop for the LOCK or TRACK to go high, they never do.

I have about 10nF main loop filter with 4.7k in series, and a 1nF bypass loop filter cap. Also my 16MHz oscillator is running nicely. Any tips?

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Re: trouble with PLL on the HC12

Edward Karpicz

> Hello; I am using an ICC12 compiler and NOICE debugger with a USB pod with
> an HC12 128kB chip running with a 16MHz crystal.
>
> My problem is that when I try to set the PLL up for about 40MHz, the code
> does not seem to work in the way it should and I can't get a LOCK - or
> even a TRACK signal.

No HC12 chip I know can run that fast. Are you talking about S12? Which one?
It must be either bad filter parts, bad connection or something wrong to
VDDPLL. Did you measure VDDPLL voltage?

>
> I have to turn off the PLLSEL bit before trying to set up the mult and
> divide registers and turning the PLL on, then looking for a LOCK signal;
> but the manual says that a write to PLLSEL is not possible if the LOCK and
> TRACK bits are zero.

By default PLLSEL is 0, you don't need to clear it. Writing one to PLLSEL is
ignored while PLL is not yet locked. You can clear this bit at any time.

>
> Does that mean a write 1, or any write? To turn PLLSEL off I need to clear
> that bit whether I am locked / tracked or not.
>
> In addition, even if I assume I can write a zero to PLLSEL, and even if I
> have wait loops after setting the mult and divide registers, and then wait
> in a loop for the LOCK or TRACK to go high, they never do.
>
> I have about 10nF main loop filter with 4.7k in series, and a 1nF bypass
> loop filter cap. Also my 16MHz oscillator is running nicely. Any tips?

Values are fine. It should work. Check if XFC pin is really connected. You
may probe it with scope. You should see DC between VDDPLL and VSSPLL. Also
what are SYNR and REFDV settings? Didn't you set them for 80MHz PLL / 40MHz
bus clock? This would be too much for S12. REFDV should be 3, SYNR - 4.for
40MHz PLL clock.

Edward


>
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>
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> Yahoo! Groups Links
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Re: trouble with PLL on the HC12

elgrip


Thanks for your reply Edward. You did hit upon more of the possible things in the hardware but here they were all OK; and it is an HC9S12DG128 chip with mask 1L59W.

Good to know that you can zero the bit at any time; the manual states only that 'writes' are disabled, which I guess means that the manual is incorrect.

I got my system to work with the CLKSEL register already at all-zeroes when entering the routine, but even so I wrote zero to the PLLWAI and the PLLSEL bits; and then it worked!

I have no idea why unless it is a mask bug (Freescale's bug list as of 2011 is at http://www.freescale.com/files/microcontrollers/doc/errata/MSE9S12DT128_1L59W.htm) which I have not heard of.



--- In [hidden email], "Edward Karpicz" <karpicz@...> wrote:

>
>
> > Hello; I am using an ICC12 compiler and NOICE debugger with a USB pod with
> > an HC12 128kB chip running with a 16MHz crystal.
> >
> > My problem is that when I try to set the PLL up for about 40MHz, the code
> > does not seem to work in the way it should and I can't get a LOCK - or
> > even a TRACK signal.
>
> No HC12 chip I know can run that fast. Are you talking about S12? Which one?
> It must be either bad filter parts, bad connection or something wrong to
> VDDPLL. Did you measure VDDPLL voltage?
>
> >
> > I have to turn off the PLLSEL bit before trying to set up the mult and
> > divide registers and turning the PLL on, then looking for a LOCK signal;
> > but the manual says that a write to PLLSEL is not possible if the LOCK and
> > TRACK bits are zero.
>
> By default PLLSEL is 0, you don't need to clear it. Writing one to PLLSEL is
> ignored while PLL is not yet locked. You can clear this bit at any time.
>
> >
> > Does that mean a write 1, or any write? To turn PLLSEL off I need to clear
> > that bit whether I am locked / tracked or not.
> >
> > In addition, even if I assume I can write a zero to PLLSEL, and even if I
> > have wait loops after setting the mult and divide registers, and then wait
> > in a loop for the LOCK or TRACK to go high, they never do.
> >
> > I have about 10nF main loop filter with 4.7k in series, and a 1nF bypass
> > loop filter cap. Also my 16MHz oscillator is running nicely. Any tips?
>
> Values are fine. It should work. Check if XFC pin is really connected. You
> may probe it with scope. You should see DC between VDDPLL and VSSPLL. Also
> what are SYNR and REFDV settings? Didn't you set them for 80MHz PLL / 40MHz
> bus clock? This would be too much for S12. REFDV should be 3, SYNR - 4.for
> 40MHz PLL clock.
>
> Edward
>
>
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
> >
>