wdebug instruction causes XLB slave error acknowledge interrupt on MCF547X.
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I want to disable the PST signals, when not debugging, to reduce RF emissions. I used the following code successfully in an MCF537X project, but when I use it on a V4 processor I get an interrupt from the XLB arbiter.
csr_data dc.w 0010110010000000b ;CSR dc.w 2,0,0 ;PCD ... lea csr_data,a0 dc.w 1111101111010000b ;wdebug.l a0 dc.w 0000000000000011b My assembler doesn't support wdebug, hence the hand coded dc.w stuff. All the code does is set the PCD bit in the BDM CSR register. The fault address is csr_data + 4, i..e. half way through the data. The fault is a slave error acknowledge. The data is correctly aligned on a four byte boundary and is certainly accessible by normal instructions. Anybody know what is going on here? TIA, Chris [hidden email] Send a post to the list. [hidden email] Join the list. [hidden email] Join the list in digest mode. [hidden email] Leave the list. |
RE: wdebug instruction causes XLB slave error acknowledge interrupt on MCF547X.
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Hi Chris,
I did a simple test using the M5474EVB Lite board running dBUG ROM
monitor:
dBUG> di 20000
00020000: 2C80 MOVE.L D0,(A6) 00020002: 0002 DC.W 0x0002 00020004: 0000 DC.W 0x0000 00020006: 0000 DC.W 0x0000 00020008: 267C 0002 0000 MOVEA.L #0x00020000,A3 0002000E: 4E71 NOP 00020010: FBD3 4E71 WDEBUG (A3) 00020014: 4E71 NOP 00020016: 4E71 NOP 00020018: 4E71 NOP 0002001A: 4E71 NOP 0002001C: 4E71 NOP 0002001E: 4E4F TRAP #0x0F 00020020: 4E71 NOP 00020022: 4E71 NOP 00020024: 4E71 NOP I set the PC to 0x20008 and issued "go" command.
Watching PSTCLK with oscope, it is running be default. After
executing the above code, it is low.
So I'm seeing it work OK.
Regards,
David
David E Seymour
From: [hidden email] [mailto:[hidden email]] On Behalf Of nop head Sent: Tuesday, April 07, 2009 9:27 AM To: Seymour David-RA2693 Subject: [ColdFire] wdebug instruction causes XLB slave error acknowledge interrupt on MCF547X. csr_data dc.w 0010110010000000b ;CSR dc.w 2,0,0 ;PCD ... lea csr_data,a0 dc.w 1111101111010000b ;wdebug.l a0 dc.w 0000000000000011b My assembler doesn't support wdebug, hence the hand coded dc.w stuff. All the code does is set the PCD bit in the BDM CSR register. The fault address is csr_data + 4, i..e. half way through the data. The fault is a slave error acknowledge. The data is correctly aligned on a four byte boundary and is certainly accessible by normal instructions. Anybody know what is going on here? TIA, Chris [hidden email] Send a post to the list. [hidden email] Join the list. [hidden email] Join the list in digest mode. [hidden email] Leave the list. [hidden email] Send a post to the list. [hidden email] Join the list. [hidden email] Join the list in digest mode. [hidden email] Leave the list. |
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Hi David,
Yes I think it kills my PSTCLK, but why does it generate an XLB interrupt? Can you look at the XLB registers as see if the status register has bit 8 set. Chris 2009/4/7 Seymour David-RA2693 <[hidden email]>
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RE: wdebug instruction causes XLB slave error acknowledge interrupt on MCF547X.
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Ouch...just got everything put away! That serves me right for once
trying to keep a clean office. Lesson learned.
Thx!!
Ok...re-ran with following code:
dBUG> di 20000
00020000: 2C80 MOVE.L D0,(A6) 00020002: 0002 DC.W 0x0002 00020004: 0000 DC.W 0x0000 00020006: 0000 DC.W 0x0000 00020008: 207C 0002 0000 MOVEA.L #0x00020000,A0 0002000E: 4E71 NOP 00020010: 4E71 NOP 00020012: FBD0 0003 WDEBUG (A0) 00020016: 4E71 NOP 00020018: 4E71 NOP 0002001A: 227C 1000 0248 MOVEA.L #0x10000248,A1 00020020: 2211 MOVE.L (A1),D1 00020022: 4E71 NOP 00020024: 4E71 NOP 00020026: 4E4F TRAP #0x0F 00020028: 37FE DC.W 0x37FE dBUG> rm pc 20008 dBUG> go dBUG> rd PC: 00020028 SR: 2004 [t.Sm.000...xnZvc] An: 00020000 10000248 00000000 00000000 00000000 00000000 00000000 03FFFFF8 Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 dBUG> Register D1 is zero so bit 8 is not setting.
Anything else for me to try?
Regards,
David
David E Seymour
From: [hidden email] [mailto:[hidden email]] On Behalf Of nop head Sent: Tuesday, April 07, 2009 4:11 PM To: Seymour David-RA2693 Subject: Re: [ColdFire] wdebug instruction causes XLB slave error acknowledge interrupt on MCF547X. Yes I think it kills my PSTCLK, but why does it generate an XLB interrupt? Can you look at the XLB registers as see if the status register has bit 8 set. Chris 2009/4/7 Seymour David-RA2693 <[hidden email]>
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David,
I assume your MBAR was at 0x10000000? Why do you have NOPs around the wdebug? I am at home at the moment. I will double check my findings tomorrow at work. I had to disable the XLB interrupt to get past the wdebug and then reset the bit in the status register before enabling the interrupt again. I can't think what would cause it. My code and data are in flash, mapped with CS0, read only. MBAR is at 80000000. Am I right to assume the WDEBUG read of the data will be in supervisor data or instruction space? Odd that the address captured by the XLB was half way through the data. Chris 2009/4/7 Seymour David-RA2693 <[hidden email]>
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RE: wdebug instruction causes XLB slave error acknowledge interrupt on MCF547X.
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Hi Chris,
Yes MBAR is 0x1000_0000.
The nop are my way of viewing the code more easily and should I need to
patch another instruction in I have room to do so.
But nop insturction does sync the pipeline and ensure writes have
completed before moving onto the next instruction so maybe that is
helping????
WDEBUG should be a supervisor instruction access.
Regards,
David
David E Seymour
From: [hidden email] [mailto:[hidden email]] On Behalf Of nop head Sent: Tuesday, April 07, 2009 5:23 PM To: Seymour David-RA2693 Subject: Re: [ColdFire] wdebug instruction causes XLB slave error acknowledge interrupt on MCF547X. I assume your MBAR was at 0x10000000? Why do you have NOPs around the wdebug? I am at home at the moment. I will double check my findings tomorrow at work. I had to disable the XLB interrupt to get past the wdebug and then reset the bit in the status register before enabling the interrupt again. I can't think what would cause it. My code and data are in flash, mapped with CS0, read only. MBAR is at 80000000. Am I right to assume the WDEBUG read of the data will be in supervisor data or instruction space? Odd that the address captured by the XLB was half way through the data. Chris 2009/4/7 Seymour David-RA2693 <[hidden email]>
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